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[Hardware][NVIDIA][kernel] Fp4 MOE quant kernel optimization (#19500)
This commit is contained in:
jiahanc
GitHub
parent
2db9044ab6
commit
294fc1e2c9
@ -231,12 +231,115 @@ __device__ uint32_t cvt_warp_fp16_to_fp4(PackedVec<Type>& vec, float SFScaleVal,
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}
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// Use UE4M3 by default.
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template <class Type, bool UE8M0_SF = false>
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template <class Type, bool UE8M0_SF = false, bool SMALL_NUM_EXPERTS = false>
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__global__ void
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#if defined(__CUDA_ARCH__) && (__CUDA_ARCH__ >= 1000)
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__launch_bounds__(512, 4) cvt_fp16_to_fp4(
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#else
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cvt_fp16_to_fp4(
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#endif
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int32_t numRows, int32_t numCols, Type const* in, float const* SFScale,
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uint32_t* out, uint32_t* SFout, uint32_t* input_offset_by_experts,
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uint32_t* output_scale_offset_by_experts, int n_experts, bool low_latency) {
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#if defined(__CUDA_ARCH__) && (__CUDA_ARCH__ >= 1000)
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using PackedVec = PackedVec<Type>;
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static constexpr int CVT_FP4_NUM_THREADS_PER_SF =
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(CVT_FP4_SF_VEC_SIZE / CVT_FP4_ELTS_PER_THREAD);
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static_assert(sizeof(PackedVec) == sizeof(Type) * CVT_FP4_ELTS_PER_THREAD,
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"Vec size is not matched.");
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int tid = blockIdx.x * blockDim.x + threadIdx.x;
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int colsPerRow = numCols / CVT_FP4_ELTS_PER_THREAD;
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// Each global thread processes one element
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for (int globalIdx = tid; globalIdx < numRows * colsPerRow;
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globalIdx += gridDim.x * blockDim.x) {
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// Calculate which row and column this global thread should process
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int rowIdx = globalIdx / colsPerRow;
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int colIdx = globalIdx % colsPerRow;
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int64_t inOffset = rowIdx * colsPerRow + colIdx;
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PackedVec in_vec = reinterpret_cast<PackedVec const*>(in)[inOffset];
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// Get the output tensor offset.
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// Same as inOffset because 8 elements are packed into one uint32_t.
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int64_t outOffset = inOffset;
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auto& out_pos = out[outOffset];
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// Find index within the experts using different strategies based on expert
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// count
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int rowIdx_in_expert = 0;
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int expert_idx = 0;
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if constexpr (SMALL_NUM_EXPERTS) {
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for (int i = 0; i < n_experts; i++) {
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uint32_t current_offset = __ldca(&input_offset_by_experts[i]);
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uint32_t next_offset = __ldca(&input_offset_by_experts[i + 1]);
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if (rowIdx >= current_offset && rowIdx < next_offset) {
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rowIdx_in_expert = rowIdx - current_offset;
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expert_idx = i;
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break;
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}
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}
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} else {
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// Load input offsets into registers first, then do the computation.
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// Local array size set to 17 because of register limit.
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uint32_t local_offsets[17];
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for (int chunk_start = 0; chunk_start < n_experts; chunk_start += 16) {
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*reinterpret_cast<int4*>(local_offsets) =
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__ldca(reinterpret_cast<const int4*>(
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&input_offset_by_experts[chunk_start]));
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*reinterpret_cast<int4*>(local_offsets + 4) =
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__ldca(reinterpret_cast<const int4*>(
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&input_offset_by_experts[chunk_start + 4]));
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*reinterpret_cast<int4*>(local_offsets + 8) =
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__ldca(reinterpret_cast<const int4*>(
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&input_offset_by_experts[chunk_start + 8]));
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*reinterpret_cast<int4*>(local_offsets + 12) =
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__ldca(reinterpret_cast<const int4*>(
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&input_offset_by_experts[chunk_start + 12]));
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local_offsets[16] = __ldca(&input_offset_by_experts[chunk_start + 16]);
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// Check against the 16 loaded offsets
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#pragma unroll
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for (int i = 0; i < 16; i++) {
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if (rowIdx >= local_offsets[i] && rowIdx < local_offsets[i + 1]) {
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rowIdx_in_expert = rowIdx - local_offsets[i];
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expert_idx = chunk_start + i;
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break;
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}
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}
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}
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}
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// Get the global scaling factor, which will be applied to the SF.
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// Note SFScale is the same as next GEMM's alpha, which is
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// (448.f / (Alpha_A / 6.f)).
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float const SFScaleVal = SFScale == nullptr ? 1.0f : SFScale[expert_idx];
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int factor = CVT_FP4_SF_VEC_SIZE * 4;
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// The actual output_scales dim is computed from the padded numCols.
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int32_t numCols_padded = (numCols + factor - 1) / factor * factor;
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int numCols_SFout = numCols_padded / CVT_FP4_SF_VEC_SIZE / 4;
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uint32_t* SFout_in_expert =
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SFout + output_scale_offset_by_experts[expert_idx] * numCols_SFout;
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auto sf_out =
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cvt_quant_to_fp4_get_sf_out_offset<uint32_t,
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CVT_FP4_NUM_THREADS_PER_SF>(
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rowIdx_in_expert, colIdx, numCols, SFout_in_expert);
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out_pos = cvt_warp_fp16_to_fp4<Type, UE8M0_SF>(in_vec, SFScaleVal, sf_out);
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}
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#endif
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}
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// Kernel for LARGE_M_TOPK = true (large m_topk optimized version)
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template <class Type, bool UE8M0_SF = false, bool SMALL_NUM_EXPERTS = false>
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__global__ void
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#if defined(__CUDA_ARCH__) && (__CUDA_ARCH__ >= 1000)
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__launch_bounds__(1024, 4) cvt_fp16_to_fp4(
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#else
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cvt_fp16_to_fp4(
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#endif
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int32_t numRows, int32_t numCols, Type const* in, float const* SFScale,
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uint32_t* out, uint32_t* SFout, uint32_t* input_offset_by_experts,
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@ -247,50 +350,80 @@ cvt_fp16_to_fp4(
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(CVT_FP4_SF_VEC_SIZE / CVT_FP4_ELTS_PER_THREAD);
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static_assert(sizeof(PackedVec) == sizeof(Type) * CVT_FP4_ELTS_PER_THREAD,
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"Vec size is not matched.");
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extern __shared__ uint32_t shared_input_offsets[];
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// Input tensor row/col loops.
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for (int rowIdx = blockIdx.x; rowIdx < numRows; rowIdx += gridDim.x) {
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for (int colIdx = threadIdx.x; colIdx < numCols / CVT_FP4_ELTS_PER_THREAD;
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colIdx += blockDim.x) {
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int64_t inOffset = rowIdx * (numCols / CVT_FP4_ELTS_PER_THREAD) + colIdx;
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PackedVec in_vec = reinterpret_cast<PackedVec const*>(in)[inOffset];
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// Get the output tensor offset.
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// Same as inOffset because 8 elements are packed into one uint32_t.
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int64_t outOffset = inOffset;
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auto& out_pos = out[outOffset];
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// Find index within the experts.
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int rowIdx_in_expert = 0;
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int expert_idx = 0;
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for (int i = 0; i < n_experts; i++) {
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if (rowIdx >= input_offset_by_experts[i] &&
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rowIdx < input_offset_by_experts[i + 1]) {
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rowIdx_in_expert = rowIdx - input_offset_by_experts[i];
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expert_idx = i;
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break;
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}
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}
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// Get the global scaling factor, which will be applied to the SF.
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// Note SFScale is the same as next GEMM's alpha, which is
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// (448.f / (Alpha_A / 6.f)).
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float const SFScaleVal = SFScale == nullptr ? 1.0f : SFScale[expert_idx];
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int factor = CVT_FP4_SF_VEC_SIZE * 4;
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// The actual output_scales dim is computed from the padded numCols.
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int32_t numCols_padded = (numCols + factor - 1) / factor * factor;
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int numCols_SFout = numCols_padded / CVT_FP4_SF_VEC_SIZE / 4;
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uint32_t* SFout_in_expert =
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SFout + output_scale_offset_by_experts[expert_idx] * numCols_SFout;
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auto sf_out =
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cvt_quant_to_fp4_get_sf_out_offset<uint32_t,
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CVT_FP4_NUM_THREADS_PER_SF>(
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rowIdx_in_expert, colIdx, numCols, SFout_in_expert);
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out_pos =
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cvt_warp_fp16_to_fp4<Type, UE8M0_SF>(in_vec, SFScaleVal, sf_out);
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// Load input offsets into shared memory.
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// If n_experts is larger than 4, use vectorized int4 to save instructions.
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// If n_experts is smaller than 4, read directly.
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if constexpr (SMALL_NUM_EXPERTS) {
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for (int i = threadIdx.x; i < n_experts + 1; i += blockDim.x) {
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shared_input_offsets[i] = input_offset_by_experts[i];
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}
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} else {
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for (int i = threadIdx.x * 4; i < n_experts; i += blockDim.x * 4) {
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*reinterpret_cast<int4*>(&shared_input_offsets[i]) =
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*reinterpret_cast<const int4*>(&input_offset_by_experts[i]);
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}
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if (threadIdx.x == 0) {
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shared_input_offsets[n_experts] = input_offset_by_experts[n_experts];
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}
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}
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__syncthreads();
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int tid = blockIdx.x * blockDim.x + threadIdx.x;
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int colsPerRow = numCols / CVT_FP4_ELTS_PER_THREAD;
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// Each global thread processes one element
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for (int globalIdx = tid; globalIdx < numRows * colsPerRow;
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globalIdx += gridDim.x * blockDim.x) {
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// Calculate which row and column this global thread should process
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int rowIdx = globalIdx / colsPerRow;
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int colIdx = globalIdx % colsPerRow;
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int64_t inOffset = rowIdx * colsPerRow + colIdx;
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PackedVec in_vec = reinterpret_cast<PackedVec const*>(in)[inOffset];
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int64_t outOffset = inOffset;
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auto& out_pos = out[outOffset];
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// Find expert using binary search for better performance with large m_topk
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int rowIdx_in_expert = 0;
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int expert_idx = 0;
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// Binary search through experts using shared memory
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int left = 0, right = n_experts - 1;
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while (left <= right) {
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int mid = (left + right) / 2;
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// Get offsets: shared_input_offsets[i] corresponds to
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// input_offset_by_experts[i]
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uint32_t mid_offset = shared_input_offsets[mid];
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uint32_t next_offset = shared_input_offsets[mid + 1];
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if (rowIdx >= mid_offset && rowIdx < next_offset) {
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rowIdx_in_expert = rowIdx - mid_offset;
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expert_idx = mid;
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break;
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} else if (rowIdx < mid_offset) {
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right = mid - 1;
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} else {
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left = mid + 1;
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}
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}
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float const SFScaleVal = SFScale == nullptr ? 1.0f : SFScale[expert_idx];
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int factor = CVT_FP4_SF_VEC_SIZE * 4;
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int32_t numCols_padded = (numCols + factor - 1) / factor * factor;
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int numCols_SFout = numCols_padded / CVT_FP4_SF_VEC_SIZE / 4;
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uint32_t* SFout_in_expert =
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SFout + output_scale_offset_by_experts[expert_idx] * numCols_SFout;
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auto sf_out =
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cvt_quant_to_fp4_get_sf_out_offset<uint32_t,
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CVT_FP4_NUM_THREADS_PER_SF>(
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rowIdx_in_expert, colIdx, numCols, SFout_in_expert);
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out_pos = cvt_warp_fp16_to_fp4<Type, UE8M0_SF>(in_vec, SFScaleVal, sf_out);
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}
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#endif
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}
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@ -309,18 +442,63 @@ void quant_impl(void* output, void* output_scale, void* input,
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// Grid, Block size.
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// Each thread converts 8 values.
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dim3 block(std::min(int(k / ELTS_PER_THREAD), 512));
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int const workSizePerRow = k / ELTS_PER_THREAD;
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int const totalWorkSize = m_topk * workSizePerRow;
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dim3 block(std::min(workSizePerRow, 512));
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// Get number of blocks per SM (assume we can fully utilize the SM).
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int const numBlocksPerSM = 2048 / block.x;
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dim3 grid(std::min(int(m_topk), multiProcessorCount * numBlocksPerSM));
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dim3 grid(std::min(static_cast<int>((totalWorkSize + block.x - 1) / block.x),
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multiProcessorCount * numBlocksPerSM));
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while (grid.x <= multiProcessorCount && block.x > 64) {
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grid.x *= 2;
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block.x = (block.x + 1) / 2;
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}
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cvt_fp16_to_fp4<T, false><<<grid, block, 0, stream>>>(
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m_topk, k, reinterpret_cast<T*>(input),
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reinterpret_cast<float*>(input_global_scale),
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reinterpret_cast<uint32_t*>(output),
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reinterpret_cast<uint32_t*>(output_scale),
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reinterpret_cast<uint32_t*>(input_offset_by_experts),
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reinterpret_cast<uint32_t*>(output_scale_offset_by_experts), n_experts);
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int const blockRepeat =
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(totalWorkSize + block.x * grid.x - 1) / (block.x * grid.x);
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if (blockRepeat > 1) {
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size_t shared_mem_size = (n_experts + 1) * sizeof(uint32_t);
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if (n_experts >= 4) {
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cvt_fp16_to_fp4<T, false, false>
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<<<grid, block, shared_mem_size, stream>>>(
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m_topk, k, reinterpret_cast<T*>(input),
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reinterpret_cast<float*>(input_global_scale),
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reinterpret_cast<uint32_t*>(output),
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reinterpret_cast<uint32_t*>(output_scale),
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reinterpret_cast<uint32_t*>(input_offset_by_experts),
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reinterpret_cast<uint32_t*>(output_scale_offset_by_experts),
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n_experts);
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} else {
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cvt_fp16_to_fp4<T, false, true><<<grid, block, shared_mem_size, stream>>>(
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m_topk, k, reinterpret_cast<T*>(input),
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reinterpret_cast<float*>(input_global_scale),
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reinterpret_cast<uint32_t*>(output),
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reinterpret_cast<uint32_t*>(output_scale),
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reinterpret_cast<uint32_t*>(input_offset_by_experts),
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reinterpret_cast<uint32_t*>(output_scale_offset_by_experts),
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n_experts);
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}
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} else {
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if (n_experts >= 16) {
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cvt_fp16_to_fp4<T, false, false><<<grid, block, 0, stream>>>(
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m_topk, k, reinterpret_cast<T*>(input),
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reinterpret_cast<float*>(input_global_scale),
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reinterpret_cast<uint32_t*>(output),
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reinterpret_cast<uint32_t*>(output_scale),
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reinterpret_cast<uint32_t*>(input_offset_by_experts),
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reinterpret_cast<uint32_t*>(output_scale_offset_by_experts),
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n_experts, /* bool low_latency */ true);
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} else {
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cvt_fp16_to_fp4<T, false, true><<<grid, block, 0, stream>>>(
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m_topk, k, reinterpret_cast<T*>(input),
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reinterpret_cast<float*>(input_global_scale),
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reinterpret_cast<uint32_t*>(output),
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reinterpret_cast<uint32_t*>(output_scale),
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reinterpret_cast<uint32_t*>(input_offset_by_experts),
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reinterpret_cast<uint32_t*>(output_scale_offset_by_experts),
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n_experts, /* bool low_latency */ true);
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}
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}
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}
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/*Quantization entry for fp4 experts quantization*/
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