xinyun/vllm
1
0
Fork 0
mirror of https://git.datalinker.icu/vllm-project/vllm.git synced 2026-06-07 10:09:08 +08:00
Code Issues Packages Projects Releases Wiki Activity

[Bugfix][CI] Machete kernels: deterministic ordering for more cache hits (#23055)

Browse Source 
Signed-off-by: Andy Lo <andy@mistral.ai>
This commit is contained in:
Andy Lo 2025-08-18 07:10:26 +02:00 committed by GitHub
parent 9f1c642254
commit b2fd0b81e0
No known key found for this signature in database
GPG Key ID: B5690EEEBB952194
1 changed files with 6 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

9
csrc/quantization/machete/generate.py
View File

@ -349,9 +349,12 @@ def to_cute_constant(value: list[int]):
def unique_schedules(impl_configs: list[ImplConfig]): def unique_schedules(impl_configs: list[ImplConfig]):
return list( # Use dict over set for deterministic ordering
set(sch for impl_config in impl_configs return list({
for sch in impl_config.schedules)) sch: None
for impl_config in impl_configs
for sch in impl_config.schedules
}.keys())
def unsigned_type_with_bitwidth(num_bits): def unsigned_type_with_bitwidth(num_bits):