From bb6d43047e24f29ae5ef9d3abd4c93b447f2f0c7 Mon Sep 17 00:00:00 2001 From: ihb2032 <40718643+ihb2032@users.noreply.github.com> Date: Tue, 30 Sep 2025 21:48:07 +0800 Subject: [PATCH] [Fix] Improve CPU backend compatibility for RISC-V (#25816) Signed-off-by: lyd1992 Signed-off-by: ihb2032 <1355790728@qq.com> --- vllm/engine/arg_utils.py | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/vllm/engine/arg_utils.py b/vllm/engine/arg_utils.py index ce0f1708235f..ec61fc4b9b06 100644 --- a/vllm/engine/arg_utils.py +++ b/vllm/engine/arg_utils.py @@ -1160,11 +1160,12 @@ class EngineArgs: # Set default arguments for V1 Engine. self._set_default_args(usage_context, model_config) - # Disable chunked prefill for POWER (ppc64le)/ARM/s390x CPUs in V1 + # Disable chunked prefill for POWER (ppc64le)/ARM/s390x/RISCV CPUs in V1 if current_platform.is_cpu() and current_platform.get_cpu_architecture( - ) in (CpuArchEnum.POWERPC, CpuArchEnum.S390X, CpuArchEnum.ARM): - logger.info("Chunked prefill is not supported for ARM and POWER " - "and S390X CPUs; " + ) in (CpuArchEnum.POWERPC, CpuArchEnum.S390X, CpuArchEnum.ARM, + CpuArchEnum.RISCV): + logger.info("Chunked prefill is not supported for ARM and POWER, " + "S390X and RISC-V CPUs; " "disabling it for V1 backend.") self.enable_chunked_prefill = False assert self.enable_chunked_prefill is not None