xinyun/vllm
1
0
Fork 0
mirror of https://git.datalinker.icu/vllm-project/vllm.git synced 2025-12-09 13:15:48 +08:00
Code Issues Packages Projects Releases Wiki Activity

[Frontend] Improve the performance of is_reasoning_end (#25735)

Browse Source 
Signed-off-by: chaunceyjiang <chaunceyjiang@gmail.com>
This commit is contained in:
Chauncey 2025-10-11 10:43:39 +08:00 committed by GitHub
parent 5bc26c438d
commit be067861c6
No known key found for this signature in database
GPG Key ID: B5690EEEBB952194
1 changed files with 2 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
vllm/reasoning/basic_parsers.py
View File

@ -59,7 +59,8 @@ class BaseThinkingReasoningParser(ReasoningParser):
)
def is_reasoning_end(self, input_ids: list[int]) -> bool:
return self.end_token_id in input_ids
end_token_id = self.end_token_id
return any(input_id == end_token_id for input_id in reversed(input_ids))
def extract_content_ids(self, input_ids: list[int]) -> list[int]:
"""