Jee Jee Li
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a7b8788d2c
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[Misc] Modify the organization of GLM series (#22171)
Signed-off-by: Jee Jee Li <pandaleefree@gmail.com>
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2025-08-03 23:51:20 -07:00 |
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Isotr0py
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0d21b2664c
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[Bugfix] Fix OOM in language generation test (#20814)
Signed-off-by: Isotr0py <2037008807@qq.com>
Co-authored-by: gemini-code-assist[bot] <176961590+gemini-code-assist[bot]@users.noreply.github.com>
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2025-07-11 11:21:52 -07:00 |
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Li, Jiang
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7721ef1786
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[CI/Build][CPU] Fix CPU CI and remove all CPU V0 files (#20560)
Signed-off-by: jiang1.li <jiang1.li@intel.com>
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2025-07-07 22:13:44 -07:00 |
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Li, Jiang
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6cc1e7d96d
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[CPU] Update custom ops for the CPU backend (#20255)
Signed-off-by: jiang1.li <jiang1.li@intel.com>
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2025-07-01 07:25:03 +00:00 |
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Li, Jiang
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4555143ea7
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[CPU] V1 support for the CPU backend (#16441)
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2025-06-03 18:43:01 -07:00 |
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Simon Mo
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02f0c7b220
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[Misc] Add SPDX-FileCopyrightText (#19100)
Signed-off-by: simon-mo <simon.mo@hey.com>
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2025-06-03 11:20:17 -07:00 |
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TJian
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a810b5b088
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[BugFix] [ROCm]: Bugfix and handle addition case of input for rocm_aiter_rms_norm (#17857)
Signed-off-by: tjtanaa <tunjian.tan@embeddedllm.com>
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2025-05-11 04:17:11 -07:00 |
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Cyrus Leung
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887d7af882
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[Core] Gate prompt_embeds behind a feature flag (#17607)
Signed-off-by: DarkLight1337 <tlleungac@connect.ust.hk>
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2025-05-04 00:19:20 +08:00 |
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Andrew Sansom
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cc2a77d7f1
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[Core] [Bugfix] Add Input Embeddings (#15428)
Signed-off-by: Andrew Sansom <andrew@protopia.ai>
Signed-off-by: DarkLight1337 <tlleungac@connect.ust.hk>
Co-authored-by: 临景 <linjing.yx@alibaba-inc.com>
Co-authored-by: Bryce1010 <bryceyx@gmail.com>
Co-authored-by: Nan2018 <nan@protopia.ai>
Co-authored-by: Cyrus Leung <cyrus.tl.leung@gmail.com>
Co-authored-by: DarkLight1337 <tlleungac@connect.ust.hk>
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2025-05-02 01:06:39 -07:00 |
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Cyrus Leung
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48e925fab5
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[Misc] Clean up test docstrings and names (#17521)
Signed-off-by: DarkLight1337 <tlleungac@connect.ust.hk>
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2025-05-01 05:19:32 -07:00 |
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