3 Commits

Author	SHA1	Message	Date
Li, Jiang	a15a50fc17	[CPU] Enable shared-memory based pipeline parallel for CPU backend (#21289) ... Signed-off-by: jiang1.li <jiang1.li@intel.com>	2025-07-21 09:07:08 -07:00
Li, Jiang	6cc1e7d96d	[CPU] Update custom ops for the CPU backend (#20255) ... Signed-off-by: jiang1.li <jiang1.li@intel.com>	2025-07-01 07:25:03 +00:00
Li, Jiang	550b2801ad	[CPU][Bugfix] Using custom allreduce for CPU backend (#15934) ... Signed-off-by: jiang1.li <jiang1.li@intel.com>	2025-04-02 07:46:47 -07:00