Li, Jiang a15a50fc17

[CPU] Enable shared-memory based pipeline parallel for CPU backend (#21289) ...

Signed-off-by: jiang1.li <jiang1.li@intel.com>

2025-07-21 09:07:08 -07:00

..

__init__.py

[V0 deprecation] Remove V0 HPU backend (#21131)

2025-07-17 16:37:36 -07:00

cpu.py

[CPU] Enable shared-memory based pipeline parallel for CPU backend (#21289)

2025-07-21 09:07:08 -07:00

cuda.py

[V0 Deprecation] Remove V0 Spec Decode workers (#21152)

2025-07-18 21:47:50 -07:00

interface.py

[V0 Deprecation] Deprecate BlockSparse Attention & Phi3-Small (#21217)

2025-07-19 13:53:17 -07:00

neuron.py

[Refactor]Abstract Platform Interface for Distributed Backend and Add xccl Support for Intel XPU (#19410)

2025-07-07 04:32:32 +00:00

rocm.py

[V0 Deprecation] Remove V0 Spec Decode workers (#21152)

2025-07-18 21:47:50 -07:00

tpu.py

[TPU] support fp8 kv cache quantization (#19292)

2025-07-20 03:01:00 +00:00

xpu.py

[BugFix] Fix VllmConfig() construction on all platforms (#20695)

2025-07-10 07:00:20 +00:00