Pavani Majety 7bd4c37ae7

[Core] Add Flashinfer TRTLLM Backend for Flashinfer decode path (SM100). (#19825) ...

Signed-off-by: Pavani Majety <pmajety@nvidia.com>
Signed-off-by: mgoin <mgoin64@gmail.com>
Co-authored-by: shuw <shuw@nvidia.com>
Co-authored-by: mgoin <mgoin64@gmail.com>

2025-07-11 09:23:23 +00:00

..

__init__.py

[Refactor]Abstract Platform Interface for Distributed Backend and Add xccl Support for Intel XPU (#19410)

2025-07-07 04:32:32 +00:00

cpu.py

[Doc] Add engine args back in to the docs (#20674)

2025-07-10 08:02:40 -07:00

cuda.py

[Core] Add Flashinfer TRTLLM Backend for Flashinfer decode path (SM100). (#19825)

2025-07-11 09:23:23 +00:00

hpu.py

[misc]refactor Platform.set_device method (#20262)

2025-07-09 01:39:47 +00:00

interface.py

[misc]refactor Platform.set_device method (#20262)

2025-07-09 01:39:47 +00:00

neuron.py

[Refactor]Abstract Platform Interface for Distributed Backend and Add xccl Support for Intel XPU (#19410)

2025-07-07 04:32:32 +00:00

rocm.py

[ROCm][Regression] Remove tensor creation that harms performance on ROCm (#20741)

2025-07-10 09:22:23 -07:00

tpu.py

[BugFix] Fix VllmConfig() construction on all platforms (#20695)

2025-07-10 07:00:20 +00:00

xpu.py

[BugFix] Fix VllmConfig() construction on all platforms (#20695)

2025-07-10 07:00:20 +00:00