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mirror of https://git.datalinker.icu/vllm-project/vllm.git synced 2025-12-10 07:45:29 +08:00
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vllm/tests/models
History
Cyrus Leung 355f66348c
[V1] Remove legacy input registry (#15673)
Signed-off-by: DarkLight1337 <tlleungac@connect.ust.hk>
2025-03-27 23:34:34 -07:00
..
decoder_only
[FEAT][ROCm] Integrate Fused MoE Kernels from AITER (#14967)
2025-03-26 16:30:30 +08:00
embedding
[Core] Update dtype detection and defaults (#14858)
2025-03-19 13:49:33 +08:00
encoder_decoder
[Quantization][V1] BitsAndBytes support V1 (#15611)
2025-03-28 10:12:47 +08:00
fixtures
[Mistral-Small 3.1] Update docs and tests (#14977)
2025-03-18 03:29:42 -07:00
multimodal
[V1] Remove legacy input registry (#15673)
2025-03-27 23:34:34 -07:00
__init__.py
[CI/Build] Move test_utils.py to tests/utils.py (#4425)
2024-05-13 23:50:09 +09:00
registry.py
Separate base model from TransformersModel (#15467)
2025-03-26 18:13:38 +08:00
test_initialization.py
[V1] V1 Enablement Oracle (#13726)
2025-03-14 22:02:20 -07:00
test_oot_registration.py
[Bugfix][ROCm] running new process using spawn method for rocm in tests. (#14810)
2025-03-17 11:33:35 +00:00
test_registry.py
[Bugfix][ROCm] running new process using spawn method for rocm in tests. (#14810)
2025-03-17 11:33:35 +00:00
test_transformers.py
[Quantization][V1] BitsAndBytes support V1 (#15611)
2025-03-28 10:12:47 +08:00
test_vision.py
[Bugfix] Fix Positive Feature Layers in Llava Models (#13514)
2025-02-19 08:50:07 +00:00
utils.py
[Core] Update dtype detection and defaults (#14858)
2025-03-19 13:49:33 +08:00
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