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Signed-off-by: AzizCode92 <azizbenothman76@gmail.com> Signed-off-by: Aziz <azizbenothman76@gmail.com> Co-authored-by: gemini-code-assist[bot] <176961590+gemini-code-assist[bot]@users.noreply.github.com> Co-authored-by: Cyrus Leung <tlleungac@connect.ust.hk>
34 lines
1.1 KiB
Python
34 lines
1.1 KiB
Python
# SPDX-License-Identifier: Apache-2.0
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# SPDX-FileCopyrightText: Copyright contributors to the vLLM project
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from .interfaces import (HasInnerState, SupportsLoRA, SupportsMRoPE,
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SupportsMultiModal, SupportsPP, SupportsTranscription,
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SupportsV0Only, has_inner_state, supports_lora,
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supports_mrope, supports_multimodal, supports_pp,
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supports_transcription, supports_v0_only)
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from .interfaces_base import (VllmModelForPooling, VllmModelForTextGeneration,
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is_pooling_model, is_text_generation_model)
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from .registry import ModelRegistry
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__all__ = [
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"ModelRegistry",
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"VllmModelForPooling",
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"is_pooling_model",
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"VllmModelForTextGeneration",
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"is_text_generation_model",
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"HasInnerState",
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"has_inner_state",
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"SupportsLoRA",
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"supports_lora",
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"SupportsMultiModal",
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"supports_multimodal",
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"SupportsMRoPE",
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"supports_mrope",
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"SupportsPP",
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"supports_pp",
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"SupportsTranscription",
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"supports_transcription",
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"SupportsV0Only",
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"supports_v0_only",
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]
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