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vllm
/
tests
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v1
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kv_connector
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nixl_integration
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Chendi.Xue
c3e2978620
[NIXL] fix cpu PD after physical <> logical block_size PR (
#28904
)
...
Signed-off-by: Chendi Xue <chendi.xue@intel.com>
2025-11-18 14:03:23 -05:00
..
run_accuracy_test.sh
[NIXL] fix cpu PD after physical <> logical block_size PR (
#28904
)
2025-11-18 14:03:23 -05:00
run_edge_case_test.sh
[Hybrid allocator + kv connector] revert connector test changes related to hybrid allocator (
#28011
)
2025-11-05 10:36:31 +00:00
run_tpu_disagg_accuracy_test.sh
…
run_tpu_edge_case_test.sh
…
test_accuracy.py
[CI] Nixl integration tests (
#27010
)
2025-10-17 07:13:31 -07:00
test_disagg_accuracy.py
…
test_edge_cases.py
…
toy_proxy_server.py
[CI] Nixl integration tests (
#27010
)
2025-10-17 07:13:31 -07:00
tp_config_sweep_accuracy_test.sh
[CI] Nixl integration tests DP-EP (
#27199
)
2025-10-22 11:17:48 +08:00
