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Signed-off-by: elvischenv <219235043+elvischenv@users.noreply.github.com> Signed-off-by: Luka Govedič <ProExpertProg@users.noreply.github.com> Co-authored-by: Luka Govedič <ProExpertProg@users.noreply.github.com>
213 lines
8.0 KiB
Plaintext
213 lines
8.0 KiB
Plaintext
/*
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* Copyright (c) 2025, NVIDIA CORPORATION. All rights reserved.
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#include <torch/all.h>
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#include <cuda_runtime_api.h>
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#include <cuda_runtime.h>
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#include <ATen/cuda/CUDAContext.h>
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#include <c10/cuda/CUDAGuard.h>
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#include <cuda_fp8.h>
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#include "dispatch_utils.h"
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#include "cuda_utils.h"
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#include "nvfp4_utils.cuh"
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namespace vllm {
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template <class Type>
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__inline__ __device__ PackedVec<Type> compute_silu(PackedVec<Type>& vec,
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PackedVec<Type>& vec2) {
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PackedVec<Type> result;
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#pragma unroll
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for (int i = 0; i < CVT_FP4_ELTS_PER_THREAD / 2; ++i) {
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if constexpr (std::is_same_v<Type, half>) {
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half2 val(0.5f, 0.5f);
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half2 t0 = __hmul2(vec.elts[i], val);
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half2 t1 = __hfma2(h2tanh(t0), val, val);
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half2 t2 = __hmul2(vec.elts[i], t1);
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result.elts[i] = __hmul2(t2, vec2.elts[i]);
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} else {
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__nv_bfloat162 val(0.5f, 0.5f);
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__nv_bfloat162 t0 = __hmul2(vec.elts[i], val);
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__nv_bfloat162 t1 = __hfma2(h2tanh(t0), val, val);
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__nv_bfloat162 t2 = __hmul2(vec.elts[i], t1);
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result.elts[i] = __hmul2(t2, vec2.elts[i]);
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}
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}
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return result;
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}
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// Quantizes the provided PackedVec into the uint32_t output
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template <class Type, bool UE8M0_SF = false>
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__device__ uint32_t silu_and_cvt_warp_fp16_to_fp4(PackedVec<Type>& vec,
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PackedVec<Type>& vec2,
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float SFScaleVal,
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uint8_t* SFout) {
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PackedVec<Type> out_silu = compute_silu(vec, vec2);
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// Get absolute maximum values among the local 8 values.
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auto localMax = __habs2(out_silu.elts[0]);
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// Local maximum value.
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#pragma unroll
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for (int i = 1; i < CVT_FP4_ELTS_PER_THREAD / 2; i++) {
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localMax = __hmax2(localMax, __habs2(out_silu.elts[i]));
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}
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// Get the absolute maximum among all 16 values (two threads).
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localMax = __hmax2(__shfl_xor_sync(uint32_t(-1), localMax, 1), localMax);
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// Get the final absolute maximum values.
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float vecMax = float(__hmax(localMax.x, localMax.y));
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// Get the SF (max value of the vector / max value of e2m1).
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// maximum value of e2m1 = 6.0.
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// TODO: use half as compute data type.
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float SFValue = SFScaleVal * (vecMax * reciprocal_approximate_ftz(6.0f));
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// 8 bits representation of the SF.
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uint8_t fp8SFVal;
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// Write the SF to global memory (STG.8).
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if constexpr (UE8M0_SF) {
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// Extract the 8 exponent bits from float32.
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// float 32bits = 1 sign bit + 8 exponent bits + 23 mantissa bits.
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uint32_t tmp = reinterpret_cast<uint32_t&>(SFValue) >> 23;
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fp8SFVal = tmp & 0xff;
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// Convert back to fp32.
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reinterpret_cast<uint32_t&>(SFValue) = tmp << 23;
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} else {
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// Here SFValue is always positive, so E4M3 is the same as UE4M3.
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__nv_fp8_e4m3 tmp = __nv_fp8_e4m3(SFValue);
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reinterpret_cast<__nv_fp8_e4m3&>(fp8SFVal) = tmp;
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// Convert back to fp32.
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SFValue = float(tmp);
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}
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// Get the output scale.
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// Recipe: final_scale = reciprocal(fp32(fp8(SFValue * SFScaleVal))) *
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// reciprocal(SFScaleVal))
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float outputScale =
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SFValue != 0 ? reciprocal_approximate_ftz(
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SFValue * reciprocal_approximate_ftz(SFScaleVal))
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: 0.0f;
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if (SFout) {
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// Write the SF to global memory (STG.8).
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*SFout = fp8SFVal;
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}
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// Convert the input to float.
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float2 fp2Vals[CVT_FP4_ELTS_PER_THREAD / 2];
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#pragma unroll
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for (int i = 0; i < CVT_FP4_ELTS_PER_THREAD / 2; i++) {
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if constexpr (std::is_same_v<Type, half>) {
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fp2Vals[i] = __half22float2(out_silu.elts[i]);
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} else {
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fp2Vals[i] = __bfloat1622float2(out_silu.elts[i]);
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}
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fp2Vals[i].x *= outputScale;
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fp2Vals[i].y *= outputScale;
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}
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// Convert to e2m1 values.
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uint32_t e2m1Vec = fp32_vec_to_e2m1(fp2Vals);
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// Write the e2m1 values to global memory.
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return e2m1Vec;
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}
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// Use UE4M3 by default.
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template <class Type, bool UE8M0_SF = false>
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__global__ void __launch_bounds__(1024, 4)
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silu_and_cvt_fp16_to_fp4(int32_t numRows, int32_t numCols, Type const* in,
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float const* SFScale, uint32_t* out,
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uint32_t* SFout) {
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using PackedVec = PackedVec<Type>;
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static constexpr int CVT_FP4_NUM_THREADS_PER_SF =
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(CVT_FP4_SF_VEC_SIZE / CVT_FP4_ELTS_PER_THREAD);
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static_assert(sizeof(PackedVec) == sizeof(Type) * CVT_FP4_ELTS_PER_THREAD,
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"Vec size is not matched.");
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// Get the global scaling factor, which will be applied to the SF.
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// Note SFScale is the same as next GEMM's alpha, which is
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// (448.f / (Alpha_A / 6.f)).
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float const SFScaleVal = SFScale == nullptr ? 1.0f : SFScale[0];
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// Input tensor row/col loops.
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for (int rowIdx = blockIdx.x; rowIdx < numRows; rowIdx += gridDim.x) {
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for (int colIdx = threadIdx.x; colIdx < numCols / CVT_FP4_ELTS_PER_THREAD;
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colIdx += blockDim.x) {
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int64_t inOffset =
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rowIdx * (numCols * 2 / CVT_FP4_ELTS_PER_THREAD) + colIdx;
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int64_t inOffset2 = rowIdx * (numCols * 2 / CVT_FP4_ELTS_PER_THREAD) +
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numCols / CVT_FP4_ELTS_PER_THREAD + colIdx;
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PackedVec in_vec = reinterpret_cast<PackedVec const*>(in)[inOffset];
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PackedVec in_vec2 = reinterpret_cast<PackedVec const*>(in)[inOffset2];
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// Get the output tensor offset.
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// Same as inOffset because 8 elements are packed into one uint32_t.
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int64_t outOffset = rowIdx * (numCols / CVT_FP4_ELTS_PER_THREAD) + colIdx;
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;
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auto& out_pos = out[outOffset];
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auto sf_out =
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cvt_quant_to_fp4_get_sf_out_offset<uint32_t,
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CVT_FP4_NUM_THREADS_PER_SF>(
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rowIdx, colIdx, numCols, SFout);
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out_pos = silu_and_cvt_warp_fp16_to_fp4<Type, UE8M0_SF>(
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in_vec, in_vec2, SFScaleVal, sf_out);
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}
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}
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}
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} // namespace vllm
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void silu_and_mul_nvfp4_quant_sm1xxa(torch::Tensor& output, // [..., d]
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torch::Tensor& output_sf,
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torch::Tensor& input, // [..., 2 * d]
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torch::Tensor& input_sf) {
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int32_t m = input.size(0);
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int32_t n = input.size(1) / 2;
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TORCH_CHECK(n % 16 == 0, "The N dimension must be multiple of 16.");
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TORCH_CHECK(input.scalar_type() == at::ScalarType::Half ||
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input.scalar_type() == at::ScalarType::BFloat16,
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"Unsupported input data type for quantize_to_fp4.");
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int multiProcessorCount =
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get_device_attribute(cudaDevAttrMultiProcessorCount, -1);
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auto input_sf_ptr = static_cast<float const*>(input_sf.data_ptr());
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auto sf_out = static_cast<int32_t*>(output_sf.data_ptr());
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auto output_ptr = static_cast<int64_t*>(output.data_ptr());
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const at::cuda::OptionalCUDAGuard device_guard(device_of(input));
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auto stream = at::cuda::getCurrentCUDAStream(input.get_device());
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dim3 block(std::min(int(n / ELTS_PER_THREAD), 1024));
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int const numBlocksPerSM = 2048 / block.x;
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dim3 grid(std::min(int(m), multiProcessorCount * numBlocksPerSM));
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VLLM_DISPATCH_HALF_TYPES(
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input.scalar_type(), "silu_and_mul_nvfp4_quant_kernel", [&] {
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using cuda_type = vllm::CUDATypeConverter<scalar_t>::Type;
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auto input_ptr = static_cast<cuda_type const*>(input.data_ptr());
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vllm::silu_and_cvt_fp16_to_fp4<cuda_type><<<grid, block, 0, stream>>>(
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m, n, input_ptr, input_sf_ptr,
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reinterpret_cast<uint32_t*>(output_ptr),
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reinterpret_cast<uint32_t*>(sf_out));
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});
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}
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