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vllm/vllm/attention
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Thien Tran 4f044b1d67
[Kernel][CPU] CPU MLA (#14744) 
Signed-off-by: Thien Tran <gau.nernst@yahoo.com.sg>
2025-03-25 09:34:59 +00:00
..
backends
[Kernel][CPU] CPU MLA (#14744)
2025-03-25 09:34:59 +00:00
ops
[Kernel] [V1] Further optimizations to ROCm (Triton) Backend to better handle GQA. (#14431)
2025-03-13 20:42:27 -07:00
__init__.py
[Attention] Flash Attention 3 - fp8 (#14570)
2025-03-20 01:14:20 -04:00
layer.py
[TPU][V1] MHA Pallas backend (#15288)
2025-03-21 08:50:39 -07:00
selector.py
Correct capitalisation: VLLM -> vLLM (#14562)
2025-03-10 16:36:21 +00:00