This website requires JavaScript.
Explore
Help
Sign In
xinyun
/
vllm
Watch
1
Star
0
Fork
0
You've already forked vllm
mirror of
https://git.datalinker.icu/vllm-project/vllm.git
synced
2025-12-17 10:25:01 +08:00
Code
Issues
Packages
Projects
Releases
Wiki
Activity
vllm
/
tests
/
models
/
language
/
generation
History
TJian
a810b5b088
[BugFix] [ROCm]: Bugfix and handle addition case of input for
rocm_aiter_rms_norm
(
#17857
)
...
Signed-off-by: tjtanaa <tunjian.tan@embeddedllm.com>
2025-05-11 04:17:11 -07:00
..
__init__.py
[CI/Build] Reorganize models tests (
#17459
)
2025-04-30 23:03:08 -07:00
test_bart.py
[CI/Build] Reorganize models tests (
#17459
)
2025-04-30 23:03:08 -07:00
test_common.py
[BugFix] [ROCm]: Bugfix and handle addition case of input for
rocm_aiter_rms_norm
(
#17857
)
2025-05-11 04:17:11 -07:00
test_granite.py
[Misc] Clean up test docstrings and names (
#17521
)
2025-05-01 05:19:32 -07:00
test_granitemoehybrid.py
[Model] Add GraniteMoeHybrid 4.0 model (
#17497
)
2025-05-06 12:00:31 +08:00
test_hybrid.py
[Model] Add GraniteMoeHybrid 4.0 model (
#17497
)
2025-05-06 12:00:31 +08:00
test_mistral.py
[Misc] Clean up test docstrings and names (
#17521
)
2025-05-01 05:19:32 -07:00
test_phimoe.py
[Misc] Clean up test docstrings and names (
#17521
)
2025-05-01 05:19:32 -07:00
