vllm/tpu at 643622ba465f0bbcb07e1d81c60dac35ed994ebf - vllm

mirror of https://git.datalinker.icu/vllm-project/vllm.git synced 2025-12-09 23:54:56 +08:00

History

Akshat Tripathi 643622ba46

[Hardware][TPU][V1] Multi-LoRA Optimisations for the V1 TPU backend (#15655 )

Signed-off-by: Akshat Tripathi <akshat@krai.ai>
Signed-off-by: Chengji Yao <chengjiyao@google.com>
Signed-off-by: xihajun <junfan@krai.ai>
Signed-off-by: Jorge de Freitas <jorge.de-freitas22@imperial.ac.uk>
Signed-off-by: Jorge de Freitas <jorge@krai.ai>
Co-authored-by: Chengji Yao <chengjiyao@google.com>
Co-authored-by: xihajun <junfan@krai.ai>
Co-authored-by: Jorge de Freitas <jorge.de-freitas22@imperial.ac.uk>
Co-authored-by: Jorge de Freitas <jorge@krai.ai>

2025-05-28 19:59:09 +00:00

lora

[Hardware][TPU][V1] Multi-LoRA Optimisations for the V1 TPU backend (#15655 )

2025-05-28 19:59:09 +00:00

__init__.py

[torch.compile] avoid Dynamo guard evaluation overhead (#7898 )

2024-08-28 16:10:12 -07:00

test_compilation.py

[TPU][V1] Refine tpu_model_runner to mitigate future recompilation issues (#16275 )

2025-04-09 18:51:51 -06:00

test_custom_dispatcher.py

[V1] TPU - Fix CI/CD runner (#14974 )