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vllm/tests/models
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Li, Jiang 7721ef1786
[CI/Build][CPU] Fix CPU CI and remove all CPU V0 files (#20560)
Signed-off-by: jiang1.li <jiang1.li@intel.com>
2025-07-07 22:13:44 -07:00
..
fixtures
[Mistral-Small 3.1] Update docs and tests (#14977)
2025-03-18 03:29:42 -07:00
language
[CI/Build][CPU] Fix CPU CI and remove all CPU V0 files (#20560)
2025-07-07 22:13:44 -07:00
multimodal
[V1] Support any head size for FlexAttention backend (#20467)
2025-07-06 09:54:36 -07:00
quantization
[V1] Support any head size for FlexAttention backend (#20467)
2025-07-06 09:54:36 -07:00
__init__.py
[CI/Build] Move test_utils.py to tests/utils.py (#4425)
2024-05-13 23:50:09 +09:00
registry.py
[Model][Last/4] Automatic conversion of CrossEncoding model (#19675)
2025-07-07 14:46:04 +00:00
test_initialization.py
[V1] Support any head size for FlexAttention backend (#20467)
2025-07-06 09:54:36 -07:00
test_oot_registration.py
[CI Failure] Fix OOM with test_oot_registration_embedding (#20144)
2025-06-27 11:21:04 +08:00
test_registry.py
[Model][2/N] Automatic conversion of CrossEncoding model (#19978)
2025-07-03 13:59:23 +00:00
test_transformers.py
[Misc] Add SPDX-FileCopyrightText (#19100)
2025-06-03 11:20:17 -07:00
test_utils.py
[Misc] Add SPDX-FileCopyrightText (#19100)
2025-06-03 11:20:17 -07:00
test_vision.py
[Misc] Add SPDX-FileCopyrightText (#19100)
2025-06-03 11:20:17 -07:00
utils.py
[CI] Add mteb testing for rerank models (#19344)
2025-06-16 01:36:43 -07:00
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