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vllm
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vllm
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Li, Jiang
7f0367109e
[CI/Build][CPU] Enable cross compilation in CPU release pipeline (
#20423
)
...
Signed-off-by: jiang1.li <jiang1.li@intel.com>
2025-07-03 05:26:12 -07:00
..
lm-eval-harness
[Misc] Add SPDX-FileCopyrightText (
#19100
)
2025-06-03 11:20:17 -07:00
nightly-benchmarks
Enable CPU nightly performance benchmark and its Markdown report (
#18444
)
2025-07-02 17:50:25 -07:00
scripts
[TPU] Add a case to cover RedHatAI/Meta-Llama-3.1-8B-Instruct-quantized.w8a8 (
#20385
)
2025-07-03 06:46:41 +00:00
check-wheel-size.py
[Misc] Add SPDX-FileCopyrightText (
#19100
)
2025-06-03 11:20:17 -07:00
generate_index.py
[Misc] Add SPDX-FileCopyrightText (
#19100
)
2025-06-03 11:20:17 -07:00
pyproject.toml
[Doc] Move examples and further reorganize user guide (
#18666
)
2025-05-26 07:38:04 -07:00
release-pipeline.yaml
[CI/Build][CPU] Enable cross compilation in CPU release pipeline (
#20423
)
2025-07-03 05:26:12 -07:00
test-pipeline.yaml
[DP] Support external DP Load Balancer mode (
#19790
)
2025-07-02 10:21:52 -07:00
