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xinyun
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vllm
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vllm
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vllm
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v1
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sample
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Zhang Xiangze
7bdb42b2f2
[CPU]Avoid repeated random sample compile (
#28260
)
...
Signed-off-by: Zhang Xiangze <Xiangze.Zhang@arm.com>
2025-11-07 11:03:57 +00:00
..
logits_processor
[Bugfix] Validate custom logits processor xargs for online serving (
#27560
)
2025-11-05 16:53:33 +00:00
ops
[CPU]Avoid repeated random sample compile (
#28260
)
2025-11-07 11:03:57 +00:00
tpu
…
__init__.py
…
metadata.py
…
rejection_sampler.py
[V1][spec decode] return logprobs for spec decoding (
#26060
)
2025-10-22 22:59:59 -07:00
sampler.py
[Chore] Separate out
vllm.utils.platform_utils.py
(
#27374
)
2025-10-23 19:08:06 +00:00
