Li, Jiang a15a50fc17

[CPU] Enable shared-memory based pipeline parallel for CPU backend (#21289) ...

Signed-off-by: jiang1.li <jiang1.li@intel.com>

2025-07-21 09:07:08 -07:00

..

sgl-kernels

[CI] update typos config for CI pre-commit and fix some spells (#20919)

2025-07-15 21:12:40 -07:00

activation.cpp

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attention.cpp

[CI] change spell checker from codespell to typos (#18711)

2025-06-11 19:57:10 -07:00

cache.cpp

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cpu_types_arm.hpp

[Hardware][CPU] Vllm int8 quantization enablement for ARM CPU (#14129)

2025-07-10 15:59:04 +00:00

cpu_types_vsx.hpp

[Hardware][Power] Enable compressed tensor W8A8 INT8 quantization for POWER (#17153)

2025-05-07 22:35:03 -07:00

cpu_types_vxe.hpp

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cpu_types_x86.hpp

[CI] change spell checker from codespell to typos (#18711)

2025-06-11 19:57:10 -07:00

cpu_types.hpp

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dnnl_helper.hpp

[Hardware][CPU] Vllm int8 quantization enablement for ARM CPU (#14129)

2025-07-10 15:59:04 +00:00

layernorm.cpp

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mla_decode.cpp

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pos_encoding.cpp

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quant.cpp

[Hardware][CPU] Vllm int8 quantization enablement for ARM CPU (#14129)

2025-07-10 15:59:04 +00:00

shm.cpp

[CPU] Enable shared-memory based pipeline parallel for CPU backend (#21289)

2025-07-21 09:07:08 -07:00

torch_bindings.cpp

[Hardware][CPU] Vllm int8 quantization enablement for ARM CPU (#14129)

2025-07-10 15:59:04 +00:00

utils.cpp

Support no privileged mode on CPU for docker and kubernetes deployments (#19241)

2025-06-11 04:11:47 -07:00