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vllm
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vllm
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vllm
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v1
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Jialin Ouyang
a32237665d
[Core] Optimize update checks in LogitsProcessor (
#21245
)
...
Signed-off-by: Jialin Ouyang <Jialin.Ouyang@gmail.com>
2025-07-22 05:27:18 -07:00
..
ops
[v1][sampler] Inplace logprobs comparison to get the token rank (
#21283
)
2025-07-21 13:47:47 -07:00
tpu
[V1] Decouple GPU and TPU
InputBatch
(
#19778
)
2025-06-18 06:38:13 +00:00
__init__.py
[V1] Implement vLLM V1 [1/N] (
#9289
)
2024-10-22 01:24:07 -07:00
logits_processor.py
[Core] Optimize update checks in LogitsProcessor (
#21245
)
2025-07-22 05:27:18 -07:00
metadata.py
[V1] LogitsProcessor programming model (
#16728
)
2025-07-02 09:10:42 -07:00
rejection_sampler.py
[Misc] Add SPDX-FileCopyrightText (
#19100
)
2025-06-03 11:20:17 -07:00
sampler.py
[v1][sampler] Inplace logprobs comparison to get the token rank (
#21283
)
2025-07-21 13:47:47 -07:00
