chenlang a88371f84e [Hardware][RISC-V] Add riscv64 support for vLLM with scalar (#22112) ...

Signed-off-by: chenlang <chen.lang5@zte.com.cn>
Co-authored-by: chenlang <10346245@zte.com.cn>
Signed-off-by: yewentao256 <zhyanwentao@126.com>

2025-10-03 13:35:55 -07:00

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sgl-kernels

[Doc]: fix typos in various files (#24726)

2025-09-12 06:43:12 -07:00

activation.cpp

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attention.cpp

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cache.cpp

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cpu_types_arm.hpp

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cpu_types_scalar.hpp

[Hardware][RISC-V] Add riscv64 support for vLLM with scalar (#22112)

2025-10-03 13:35:55 -07:00

cpu_types_vsx.hpp

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cpu_types_vxe.hpp

[Doc]: fix typos in various files (#24726)

2025-09-12 06:43:12 -07:00

cpu_types_x86.hpp

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cpu_types.hpp

[Hardware][RISC-V] Add riscv64 support for vLLM with scalar (#22112)

2025-10-03 13:35:55 -07:00

dnnl_helper.cpp

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dnnl_helper.h

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dnnl_kernels.cpp

[Bugfix] Fix Stream usage in CPU model runner and OneDNN kernel check (#25046)

2025-09-17 05:54:02 -07:00

float_convert.hpp

[Hardware][RISC-V] Add riscv64 support for vLLM with scalar (#22112)

2025-10-03 13:35:55 -07:00

layernorm.cpp

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mla_decode.cpp

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pos_encoding.cpp

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shm.cpp

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torch_bindings.cpp

[fix]: add Arm 4bit fused moe support (#23809)

2025-10-03 13:35:54 -07:00

utils.cpp

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