mirror of
https://git.datalinker.icu/vllm-project/vllm.git
synced 2025-12-16 11:46:00 +08:00
404 lines
14 KiB
Plaintext
404 lines
14 KiB
Plaintext
#include <torch/all.h>
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#include <ATen/cuda/CUDAContext.h>
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#include <c10/cuda/CUDAGuard.h>
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#include <cuda_runtime.h>
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#include <cuda_fp8.h>
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template <typename T>
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struct TypeConverter {
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using Type = half2;
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}; // keep for generality
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template <>
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struct TypeConverter<half2> {
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using Type = half;
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};
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template <>
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struct TypeConverter<half> {
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using Type = half2;
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};
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template <>
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struct TypeConverter<__nv_bfloat162> {
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using Type = __nv_bfloat16;
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};
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template <>
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struct TypeConverter<__nv_bfloat16> {
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using Type = __nv_bfloat162;
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};
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#define ELTS_PER_THREAD 8
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constexpr int CVT_FP4_ELTS_PER_THREAD = 8;
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constexpr int CVT_FP4_SF_VEC_SIZE = 16;
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// Convert 8 float32 values into 8 e2m1 values (represented as one uint32_t).
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inline __device__ uint32_t fp32_vec_to_e2m1(float (&array)[8]) {
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#if defined(__CUDA_ARCH__) && (__CUDA_ARCH__ >= 1000)
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uint32_t val;
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asm volatile(
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"{\n"
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".reg .b8 byte0;\n"
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".reg .b8 byte1;\n"
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".reg .b8 byte2;\n"
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".reg .b8 byte3;\n"
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"cvt.rn.satfinite.e2m1x2.f32 byte0, %2, %1;\n"
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"cvt.rn.satfinite.e2m1x2.f32 byte1, %4, %3;\n"
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"cvt.rn.satfinite.e2m1x2.f32 byte2, %6, %5;\n"
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"cvt.rn.satfinite.e2m1x2.f32 byte3, %8, %7;\n"
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"mov.b32 %0, {byte0, byte1, byte2, byte3};\n"
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"}"
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: "=r"(val)
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: "f"(array[0]), "f"(array[1]), "f"(array[2]), "f"(array[3]),
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"f"(array[4]), "f"(array[5]), "f"(array[6]), "f"(array[7]));
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return val;
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#else
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return 0;
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#endif
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}
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// Convert 4 float2 values into 8 e2m1 values (represented as one uint32_t).
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inline __device__ uint32_t fp32_vec_to_e2m1(float2 (&array)[4]) {
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#if defined(__CUDA_ARCH__) && (__CUDA_ARCH__ >= 1000)
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uint32_t val;
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asm volatile(
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"{\n"
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".reg .b8 byte0;\n"
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".reg .b8 byte1;\n"
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".reg .b8 byte2;\n"
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".reg .b8 byte3;\n"
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"cvt.rn.satfinite.e2m1x2.f32 byte0, %2, %1;\n"
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"cvt.rn.satfinite.e2m1x2.f32 byte1, %4, %3;\n"
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"cvt.rn.satfinite.e2m1x2.f32 byte2, %6, %5;\n"
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"cvt.rn.satfinite.e2m1x2.f32 byte3, %8, %7;\n"
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"mov.b32 %0, {byte0, byte1, byte2, byte3};\n"
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"}"
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: "=r"(val)
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: "f"(array[0].x), "f"(array[0].y), "f"(array[1].x), "f"(array[1].y),
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"f"(array[2].x), "f"(array[2].y), "f"(array[3].x), "f"(array[3].y));
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return val;
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#else
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return 0;
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#endif
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}
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// Fast reciprocal.
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inline __device__ float reciprocal_approximate_ftz(float a) {
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float b;
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asm volatile("rcp.approx.ftz.f32 %0, %1;\n" : "=f"(b) : "f"(a));
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return b;
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}
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template <class SFType, int CVT_FP4_NUM_THREADS_PER_SF>
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__device__ uint8_t* cvt_quant_to_fp4_get_sf_out_offset(int rowIdx, int colIdx,
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int numCols,
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SFType* SFout) {
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#if defined(__CUDA_ARCH__) && (__CUDA_ARCH__ >= 1000)
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static_assert(CVT_FP4_NUM_THREADS_PER_SF == 1 ||
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CVT_FP4_NUM_THREADS_PER_SF == 2);
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// One pair of threads write one SF to global memory.
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// TODO: stage through smem for packed STG.32
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// is it better than STG.8 from 4 threads ?
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if (threadIdx.x % CVT_FP4_NUM_THREADS_PER_SF == 0) {
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// SF vector index (16 elements share one SF in the K dimension).
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int32_t kIdx = colIdx / CVT_FP4_NUM_THREADS_PER_SF;
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int32_t mIdx = rowIdx;
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// SF layout [numMTiles, numKTiles, 32 (mTile), 4 (mTile), 4(kTile)]
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// --> index [mTileIdx, kTileIdx, outerMIdx, innerMIdx, innerKIdx]
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int32_t mTileIdx = mIdx / (32 * 4);
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// SF vector size 16.
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int factor = CVT_FP4_SF_VEC_SIZE * 4;
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int32_t numKTiles = (numCols + factor - 1) / factor;
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int64_t mTileStride = numKTiles * 32 * 4 * 4;
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int32_t kTileIdx = (kIdx / 4);
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int64_t kTileStride = 32 * 4 * 4;
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// M tile layout [32, 4] is column-major.
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int32_t outerMIdx = (mIdx % 32);
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int64_t outerMStride = 4 * 4;
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int32_t innerMIdx = (mIdx % (32 * 4)) / 32;
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int64_t innerMStride = 4;
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int32_t innerKIdx = (kIdx % 4);
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int64_t innerKStride = 1;
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// Compute the global offset.
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int64_t SFOffset = mTileIdx * mTileStride + kTileIdx * kTileStride +
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outerMIdx * outerMStride + innerMIdx * innerMStride +
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innerKIdx * innerKStride;
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return reinterpret_cast<uint8_t*>(SFout) + SFOffset;
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}
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#endif
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return nullptr;
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}
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// Define a 16 bytes packed data type.
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template <class Type>
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struct PackedVec {
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typename TypeConverter<Type>::Type elts[4];
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};
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template <>
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struct PackedVec<__nv_fp8_e4m3> {
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__nv_fp8x2_e4m3 elts[8];
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};
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// Quantizes the provided PackedVec into the uint32_t output
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template <class Type, bool UE8M0_SF = false>
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__device__ uint32_t cvt_warp_fp16_to_fp4(PackedVec<Type>& vec, float SFScaleVal,
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uint8_t* SFout) {
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#if defined(__CUDA_ARCH__) && (__CUDA_ARCH__ >= 1000)
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// Get absolute maximum values among the local 8 values.
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auto localMax = __habs2(vec.elts[0]);
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// Local maximum value.
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#pragma unroll
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for (int i = 1; i < CVT_FP4_ELTS_PER_THREAD / 2; i++) {
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localMax = __hmax2(localMax, __habs2(vec.elts[i]));
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}
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// Get the absolute maximum among all 16 values (two threads).
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localMax = __hmax2(__shfl_xor_sync(uint32_t(-1), localMax, 1), localMax);
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// Get the final absolute maximum values.
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float vecMax = float(__hmax(localMax.x, localMax.y));
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// Get the SF (max value of the vector / max value of e2m1).
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// maximum value of e2m1 = 6.0.
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// TODO: use half as compute data type.
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float SFValue = SFScaleVal * (vecMax * reciprocal_approximate_ftz(6.0f));
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// 8 bits representation of the SF.
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uint8_t fp8SFVal;
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// Write the SF to global memory (STG.8).
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if constexpr (UE8M0_SF) {
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// Extract the 8 exponent bits from float32.
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// float 32bits = 1 sign bit + 8 exponent bits + 23 mantissa bits.
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uint32_t tmp = reinterpret_cast<uint32_t&>(SFValue) >> 23;
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fp8SFVal = tmp & 0xff;
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// Convert back to fp32.
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reinterpret_cast<uint32_t&>(SFValue) = tmp << 23;
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} else {
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// Here SFValue is always positive, so E4M3 is the same as UE4M3.
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__nv_fp8_e4m3 tmp = __nv_fp8_e4m3(SFValue);
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reinterpret_cast<__nv_fp8_e4m3&>(fp8SFVal) = tmp;
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// Convert back to fp32.
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SFValue = float(tmp);
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}
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// Get the output scale.
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// Recipe: final_scale = reciprocal(fp32(fp8(SFValue * SFScaleVal))) *
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// reciprocal(SFScaleVal))
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float outputScale =
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SFValue != 0 ? reciprocal_approximate_ftz(
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SFValue * reciprocal_approximate_ftz(SFScaleVal))
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: 0.0f;
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if (SFout) {
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// Write the SF to global memory (STG.8).
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*SFout = fp8SFVal;
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}
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// Convert the input to float.
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float2 fp2Vals[CVT_FP4_ELTS_PER_THREAD / 2];
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#pragma unroll
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for (int i = 0; i < CVT_FP4_ELTS_PER_THREAD / 2; i++) {
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if constexpr (std::is_same_v<Type, half>) {
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fp2Vals[i] = __half22float2(vec.elts[i]);
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} else {
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fp2Vals[i] = __bfloat1622float2(vec.elts[i]);
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}
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fp2Vals[i].x *= outputScale;
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fp2Vals[i].y *= outputScale;
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}
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// Convert to e2m1 values.
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uint32_t e2m1Vec = fp32_vec_to_e2m1(fp2Vals);
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// Write the e2m1 values to global memory.
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return e2m1Vec;
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#else
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return 0;
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#endif
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}
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// Use UE4M3 by default.
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template <class Type, bool UE8M0_SF = false>
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__global__ void
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#if defined(__CUDA_ARCH__) && (__CUDA_ARCH__ >= 1000)
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__launch_bounds__(512, 4) cvt_fp16_to_fp4(
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#else
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cvt_fp16_to_fp4(
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#endif
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int32_t numRows, int32_t numCols, Type const* in, float const* SFScale,
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uint32_t* out, uint32_t* SFout, uint32_t* input_offset_by_experts,
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uint32_t* output_scale_offset_by_experts, int n_experts) {
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#if defined(__CUDA_ARCH__) && (__CUDA_ARCH__ >= 1000)
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using PackedVec = PackedVec<Type>;
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static constexpr int CVT_FP4_NUM_THREADS_PER_SF =
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(CVT_FP4_SF_VEC_SIZE / CVT_FP4_ELTS_PER_THREAD);
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static_assert(sizeof(PackedVec) == sizeof(Type) * CVT_FP4_ELTS_PER_THREAD,
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"Vec size is not matched.");
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// Input tensor row/col loops.
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for (int rowIdx = blockIdx.x; rowIdx < numRows; rowIdx += gridDim.x) {
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for (int colIdx = threadIdx.x; colIdx < numCols / CVT_FP4_ELTS_PER_THREAD;
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colIdx += blockDim.x) {
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int64_t inOffset = rowIdx * (numCols / CVT_FP4_ELTS_PER_THREAD) + colIdx;
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PackedVec in_vec = reinterpret_cast<PackedVec const*>(in)[inOffset];
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// Get the output tensor offset.
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// Same as inOffset because 8 elements are packed into one uint32_t.
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int64_t outOffset = inOffset;
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auto& out_pos = out[outOffset];
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// Find index within the experts.
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int rowIdx_in_expert = 0;
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int expert_idx = 0;
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for (int i = 0; i < n_experts; i++) {
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if (rowIdx >= input_offset_by_experts[i] &&
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rowIdx < input_offset_by_experts[i + 1]) {
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rowIdx_in_expert = rowIdx - input_offset_by_experts[i];
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expert_idx = i;
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break;
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}
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}
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// Get the global scaling factor, which will be applied to the SF.
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// Note SFScale is the same as next GEMM's alpha, which is
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// (448.f / (Alpha_A / 6.f)).
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float const SFScaleVal = SFScale == nullptr ? 1.0f : SFScale[expert_idx];
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int factor = CVT_FP4_SF_VEC_SIZE * 4;
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// The actual output_scales dim is computed from the padded numCols.
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int32_t numCols_padded = (numCols + factor - 1) / factor * factor;
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int numCols_SFout = numCols_padded / CVT_FP4_SF_VEC_SIZE / 4;
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uint32_t* SFout_in_expert =
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SFout + output_scale_offset_by_experts[expert_idx] * numCols_SFout;
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auto sf_out =
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cvt_quant_to_fp4_get_sf_out_offset<uint32_t,
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CVT_FP4_NUM_THREADS_PER_SF>(
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rowIdx_in_expert, colIdx, numCols, SFout_in_expert);
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out_pos =
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cvt_warp_fp16_to_fp4<Type, UE8M0_SF>(in_vec, SFScaleVal, sf_out);
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}
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}
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#endif
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}
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template <typename T>
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void quant_impl(void* output, void* output_scale, void* input,
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void* input_global_scale, void* input_offset_by_experts,
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void* output_scale_offset_by_experts, int m_topk, int k,
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int n_experts, cudaStream_t stream) {
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// TODO: this multiProcessorCount should be cached.
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int device;
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cudaGetDevice(&device);
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int multiProcessorCount;
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cudaDeviceGetAttribute(&multiProcessorCount, cudaDevAttrMultiProcessorCount,
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device);
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// Grid, Block size.
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// Each thread converts 8 values.
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dim3 block(std::min(int(k / ELTS_PER_THREAD), 512));
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// Get number of blocks per SM (assume we can fully utilize the SM).
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int const numBlocksPerSM = 2048 / block.x;
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dim3 grid(std::min(int(m_topk), multiProcessorCount * numBlocksPerSM));
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cvt_fp16_to_fp4<T, false><<<grid, block, 0, stream>>>(
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m_topk, k, reinterpret_cast<T*>(input),
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reinterpret_cast<float*>(input_global_scale),
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reinterpret_cast<uint32_t*>(output),
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reinterpret_cast<uint32_t*>(output_scale),
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reinterpret_cast<uint32_t*>(input_offset_by_experts),
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reinterpret_cast<uint32_t*>(output_scale_offset_by_experts), n_experts);
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}
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/*Quantization entry for fp4 experts quantization*/
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#define CHECK_TH_CUDA(x, m) TORCH_CHECK(x.is_cuda(), m, "must be a CUDA tensor")
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#define CHECK_CONTIGUOUS(x, m) \
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TORCH_CHECK(x.is_contiguous(), m, "must be contiguous")
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#define CHECK_INPUT(x, m) \
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CHECK_TH_CUDA(x, m); \
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CHECK_CONTIGUOUS(x, m);
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constexpr auto HALF = at::ScalarType::Half;
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constexpr auto BF16 = at::ScalarType::BFloat16;
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constexpr auto FLOAT = at::ScalarType::Float;
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constexpr auto INT = at::ScalarType::Int;
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constexpr auto UINT8 = at::ScalarType::Byte;
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void scaled_fp4_experts_quant_sm100a(
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torch::Tensor& output, torch::Tensor& output_scale,
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torch::Tensor const& input, torch::Tensor const& input_global_scale,
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torch::Tensor const& input_offset_by_experts,
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torch::Tensor const& output_scale_offset_by_experts) {
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CHECK_INPUT(output, "output must be a CUDA tensor");
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CHECK_INPUT(output_scale, "output_scale must be a CUDA tensor");
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CHECK_INPUT(input, "input must be a CUDA tensor");
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CHECK_INPUT(input_global_scale, "input_global_scale must be a CUDA tensor");
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CHECK_INPUT(input_offset_by_experts,
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"input_offset_by_experts must be a CUDA tensor");
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CHECK_INPUT(output_scale_offset_by_experts,
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"output_scale_offset_by_experts must be a CUDA tensor");
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TORCH_CHECK(output.dim() == 2);
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TORCH_CHECK(output_scale.dim() == 2);
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TORCH_CHECK(input.dim() == 2);
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TORCH_CHECK(input_global_scale.dim() == 1);
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TORCH_CHECK(input_offset_by_experts.dim() == 1);
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TORCH_CHECK(output_scale_offset_by_experts.dim() == 1);
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TORCH_CHECK(input.scalar_type() == HALF || input.scalar_type() == BF16);
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TORCH_CHECK(input_global_scale.scalar_type() == FLOAT);
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TORCH_CHECK(input_offset_by_experts.scalar_type() == INT);
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TORCH_CHECK(output_scale_offset_by_experts.scalar_type() == INT);
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// output is uint8 (two nvfp4 values are packed into one uint8)
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// output_scale is int32 (four fp8 values are packed into one int32)
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TORCH_CHECK(output.scalar_type() == UINT8);
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TORCH_CHECK(output_scale.scalar_type() == INT);
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const int BLOCK_SIZE = 16;
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auto m_topk = input.size(0);
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auto k = input.size(1);
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TORCH_CHECK(k % BLOCK_SIZE == 0, "k must be a multiple of 16");
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auto n_experts = input_global_scale.size(0);
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TORCH_CHECK(input_offset_by_experts.size(0) == n_experts + 1);
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TORCH_CHECK(output_scale_offset_by_experts.size(0) == n_experts + 1);
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TORCH_CHECK(output.size(0) == m_topk);
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TORCH_CHECK(output.size(1) == k / 2);
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int scales_k = k / BLOCK_SIZE;
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// 4 means the swizzle requirement by nvidia nvfp4.
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int padded_k = (scales_k + (4 - 1)) / 4 * 4;
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// 4 means 4 fp8 values are packed into one int32
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TORCH_CHECK(output_scale.size(1) * 4 == padded_k);
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auto in_dtype = input.dtype();
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at::cuda::CUDAGuard device_guard{(char)input.get_device()};
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const cudaStream_t stream =
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at::cuda::getCurrentCUDAStream(input.get_device());
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if (in_dtype == at::ScalarType::Half) {
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quant_impl<half>(output.data_ptr(), output_scale.data_ptr(),
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input.data_ptr(), input_global_scale.data_ptr(),
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input_offset_by_experts.data_ptr(),
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output_scale_offset_by_experts.data_ptr(), m_topk, k,
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n_experts, stream);
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} else if (in_dtype == at::ScalarType::BFloat16) {
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quant_impl<__nv_bfloat16>(output.data_ptr(), output_scale.data_ptr(),
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input.data_ptr(), input_global_scale.data_ptr(),
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input_offset_by_experts.data_ptr(),
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output_scale_offset_by_experts.data_ptr(), m_topk,
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k, n_experts, stream);
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} else {
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TORCH_CHECK(false, "Expected input data type to be half or bfloat16");
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}
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} |