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xinyun
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vllm
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vllm
/
tests
/
basic_correctness
History
Li, Jiang
a2ae496589
[CPU] Support FP8 KV cache (
#14741
)
...
Signed-off-by: jiang1.li <jiang1.li@intel.com>
2025-03-14 22:07:36 -07:00
..
__init__.py
[CI/Build] Move
test_utils.py
to
tests/utils.py
(
#4425
)
2024-05-13 23:50:09 +09:00
test_basic_correctness.py
[misc] Rename Ray ADAG to Compiled Graph (
#13928
)
2025-02-26 20:03:28 -08:00
test_chunked_prefill.py
[CPU] Support FP8 KV cache (
#14741
)
2025-03-14 22:07:36 -07:00
test_cpu_offload.py
[V1] V1 Enablement Oracle (
#13726
)
2025-03-14 22:02:20 -07:00
test_cumem.py
[V1][Core] Fix memory issue with logits & sampling (
#14508
)
2025-03-11 04:03:41 +00:00
test_preemption.py
[V1] V1 Enablement Oracle (
#13726
)
2025-03-14 22:02:20 -07:00
