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vllm
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vllm
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vllm
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v1
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vllmellm
0af3d4f0df
[FEAT] [AITER] [ROCm] integrate aiter sampling ops (
#26084
)
...
Signed-off-by: vllmellm <vllm.ellm@embeddedllm.com>
2025-11-18 17:28:34 +00:00
..
logits_processor
[Core] Async Scheduling X Spec Decoding Compatibility (
#24799
)
2025-11-17 12:16:20 -08:00
ops
[FEAT] [AITER] [ROCm] integrate aiter sampling ops (
#26084
)
2025-11-18 17:28:34 +00:00
tpu
[V1][Spec Decode] Fix greedy temperature detection after sampler refactor (
#27077
)
2025-10-17 13:27:47 -07:00
__init__.py
…
metadata.py
…
rejection_sampler.py
[Redo]
#26368
(
#28771
)
2025-11-14 22:47:41 -08:00
sampler.py
[Chore] Separate out
vllm.utils.platform_utils.py
(
#27374
)
2025-10-23 19:08:06 +00:00
