Li, Jiang 9693dd0fe3

[CI/Build] Add x86 CPU wheel release pipeline (#28848) ...

Signed-off-by: jiang1.li <jiang1.li@intel.com>

2025-12-12 19:21:35 +00:00

..

image_build

[ci] Refactor CI file structure (#29343)

2025-12-08 17:25:43 -09:00

lm-eval-harness

[CI/Build][AMD] Add Llama4 Maverick FP8 to AMD CI (#28695)

2025-12-04 16:07:20 -08:00

performance-benchmarks

[vLLM Benchmark Suite] Add default parameters section and update CPU benchmark cases (#29381)

2025-12-02 09:00:23 +00:00

scripts

[CI] refine more logic when generating and using nightly wheels & indices, add cuda130 build for aarch64, specify correct manylinux version (#30341)

2025-12-12 00:42:30 +08:00

test_areas

[ci] Refactor CI file structure (#29343)

2025-12-08 17:25:43 -09:00

check-wheel-size.py

…

ci_config.yaml

[ci] Refactor CI file structure (#29343)

2025-12-08 17:25:43 -09:00

release-pipeline.yaml

[CI/Build] Add x86 CPU wheel release pipeline (#28848)

2025-12-12 19:21:35 +00:00

test-amd.yaml

[ROCm][CI] Use mi325_4 agent pool for V1 e2e tests (#30526)

2025-12-12 01:37:24 +00:00

test-pipeline.yaml

[ROCm] Enable Triton ScaledMM fallback + kernel selection fix (#26668)

2025-12-12 13:28:20 -05:00