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xinyun
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vllm
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vllm
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Li, Jiang
7f829be7d3
[CPU] Refactor CPU attention backend (
#27954
)
...
Signed-off-by: jiang1.li <jiang1.li@intel.com>
2025-11-12 09:43:06 +08:00
..
generation
[CPU] Refactor CPU attention backend (
#27954
)
2025-11-12 09:43:06 +08:00
generation_ppl_test
[Model][0/N] Improve all pooling task | clean up (
#25817
)
2025-10-13 16:44:50 +08:00
pooling
[CPU] Refactor CPU attention backend (
#27954
)
2025-11-12 09:43:06 +08:00
pooling_mteb_test
[Bugfix] Fix out of bound index issue for Jina-embedding-v3 RoPE with cuda graph (
#26687
)
2025-10-13 03:21:48 -07:00
__init__.py
…
