Li, Jiang 7f829be7d3

[CPU] Refactor CPU attention backend (#27954) ...

Signed-off-by: jiang1.li <jiang1.li@intel.com>

2025-11-12 09:43:06 +08:00

..

sgl-kernels

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activation.cpp

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cpu_attn_amx.hpp

[CPU] Refactor CPU attention backend (#27954)

2025-11-12 09:43:06 +08:00

cpu_attn_impl.hpp

[CPU] Refactor CPU attention backend (#27954)

2025-11-12 09:43:06 +08:00

cpu_attn_macros.h

[CPU] Refactor CPU attention backend (#27954)

2025-11-12 09:43:06 +08:00

cpu_attn_vec16.hpp

[CPU] Refactor CPU attention backend (#27954)

2025-11-12 09:43:06 +08:00

cpu_attn_vec.hpp

[CPU] Refactor CPU attention backend (#27954)

2025-11-12 09:43:06 +08:00

cpu_attn.cpp

[CPU] Refactor CPU attention backend (#27954)

2025-11-12 09:43:06 +08:00

cpu_types_arm.hpp

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cpu_types_scalar.hpp

[Hardware][RISC-V] Add riscv64 support for vLLM with scalar (#22112)

2025-09-25 20:46:11 +08:00

cpu_types_vsx.hpp

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cpu_types_vxe.hpp

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cpu_types_x86.hpp

[CPU] Refactor CPU attention backend (#27954)

2025-11-12 09:43:06 +08:00

cpu_types.hpp

[Hardware][RISC-V] Add riscv64 support for vLLM with scalar (#22112)

2025-09-25 20:46:11 +08:00

dnnl_helper.cpp

[CPU] Refactor CPU attention backend (#27954)

2025-11-12 09:43:06 +08:00

dnnl_helper.h

[CPU] Refactor CPU attention backend (#27954)

2025-11-12 09:43:06 +08:00

dnnl_kernels.cpp

[cpu][perf] Accelerate unquantized-linear for AArch64 through oneDNN/ACL and weight prepack (#25948)

2025-10-04 12:16:38 +08:00

float_convert.hpp

[Hardware][RISC-V] Add riscv64 support for vLLM with scalar (#22112)

2025-09-25 20:46:11 +08:00

layernorm.cpp

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mla_decode.cpp

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pos_encoding.cpp

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scratchpad_manager.cpp

[CPU] Refactor CPU attention backend (#27954)

2025-11-12 09:43:06 +08:00

scratchpad_manager.h

[CPU] Refactor CPU attention backend (#27954)

2025-11-12 09:43:06 +08:00

shm.cpp

[CPU] Refactor CPU attention backend (#27954)

2025-11-12 09:43:06 +08:00

torch_bindings.cpp

[CPU] Refactor CPU attention backend (#27954)

2025-11-12 09:43:06 +08:00

utils.cpp

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