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286 Commits

Author SHA1 Message Date
Woosuk Kwon
4172235ab7
[V0 deprecation] Deprecate V0 Neuron backend (#21159) 
Signed-off-by: Woosuk Kwon <woosuk.kwon@berkeley.edu>
 2025-09-06 16:15:18 -07:00
liuzhenwei
e599e2c65e
[XPU][P/D] Add XPU support in NixlConnector (#22436) 
Signed-off-by: zhenwei <zhenwei.liu@intel.com>
Co-authored-by: Kunshang Ji <kunshang.ji@intel.com>
 2025-09-04 21:03:12 -07:00
Kunshang Ji
16ded21eeb
[XPU] support Triton Attention backend on Intel GPU (#24149) 
Signed-off-by: Kunshang Ji <kunshang.ji@intel.com>
 2025-09-04 20:41:08 +08:00
Lucas Wilkinson
402759d472
[Attention] FlashAttn MLA (#14258) 
Signed-off-by: Lucas Wilkinson <lwilkinson@neuralmagic.com>
Signed-off-by: Lucas Wilkinson <lwilkins@redhat.com>
Signed-off-by: Matthew Bonanni <mbonanni001@gmail.com>
Co-authored-by: Matthew Bonanni <mbonanni001@gmail.com>
Co-authored-by: Matthew Bonanni <mbonanni@redhat.com>
 2025-09-04 02:47:59 -07:00
Matthew Bonanni
a742322092
[Attention] Blackwell FP8 MLA support with CUTLASS_MLA backend (#23289) 
Signed-off-by: Matthew Bonanni <mbonanni@redhat.com>
 2025-09-03 14:05:24 -04:00
Chaojun Zhang
862f2ef893
[XPU] Fix the bug of LoRA logits on the XPU platform (#24081) 
Signed-off-by: chzhang <chaojun.zhang@intel.com>
 2025-09-03 08:21:18 +08:00
Yan Ma
7be0cb8e9e
[XPU][Feature] fp8 online quantization support for XPU (#23148) 
Signed-off-by: Yan Ma <yan.ma@intel.com>
Co-authored-by: Qiming Zhang <qiming1.zhang@intel.com>
 2025-09-02 04:06:53 +00:00
Didier Durand
9701352e4b
[Doc]: fix typos in Python comments (#24001) 
Signed-off-by: Didier Durand <durand.didier@gmail.com>
 2025-08-31 08:21:59 +00:00
Li, Jiang
ad39106b16
[CPU] Enable data parallel for CPU backend (#23903) 
Signed-off-by: jiang1.li <jiang1.li@intel.com>
 2025-08-29 02:19:58 -07:00
Kunshang Ji
fce10dbed5
[XPU] Add xpu torch.compile support (#22609) 
Signed-off-by: Kunshang Ji <kunshang.ji@intel.com>
 2025-08-27 05:33:27 +00:00
Chaojun Zhang
8a044754bd
[XPU] Delay BF16 check to worker init for spawn compatibility (#22979) 
Signed-off-by: chzhang <chaojun.zhang@intel.com>
 2025-08-25 13:09:26 -07:00
Daifeng Li
fa78de9dc3
Quantization: support FP4 quantized models on AMD CDNA2/CDNA3 GPUs (#22527) 
Signed-off-by: feng <fengli1702@gmail.com>
Signed-off-by: Michael Goin <mgoin64@gmail.com>
Co-authored-by: Michael Goin <mgoin64@gmail.com>
 2025-08-22 20:53:21 -06:00
Matthew Bonanni
19fe1a0510
[Kernel] Add FP8 support with FlashMLA backend (#22668) 
Signed-off-by: Matthew Bonanni <mbonanni001@gmail.com>
 2025-08-22 02:26:32 +00:00
Nikhil Suryawanshi
78dba404ad
[Hardware][IBM Z]Enable v1 for s390x and s390x dockerfile fixes (#22725) 
Signed-off-by: Nikhil Suryawanshi <suryawanshin74@gmail.com>
 2025-08-19 04:40:37 +00:00
Chengji Yao
e9d6a3db69
[TPU] make ptxla not imported when using tpu_commons (#23081) 
Signed-off-by: Chengji Yao <chengjiyao@gmail.com>
Signed-off-by: Chengji Yao <chengjiyao@google.com>
Co-authored-by: Chengji Yao <chengjiyao@gmail.com>
 2025-08-19 11:46:42 +08:00
Woosuk Kwon
14006840ea
[V0 Deprecation] Remove V0 FlashInfer attention backend (#22776) 
Signed-off-by: Woosuk Kwon <woosuk.kwon@berkeley.edu>
 2025-08-18 19:54:16 -07:00
Ning Xie
08d5f7113a
[Misc] refactor function name (#23029) 
Signed-off-by: Andy Xie <andy.xning@gmail.com>
 2025-08-17 22:16:21 -07:00
Kunshang Ji
7caec10e7b
[XPU]avoid circular import during XPU init (#23017) 
Signed-off-by: Kunshang Ji <kunshang.ji@intel.com>
 2025-08-16 05:16:34 +00:00
fhl2000
74f441f4b5
[Core] Allow full cudagraph with separate attention routines and orthogonal to compilation, add support for FA2 and FlashInfer (#20059) 
Signed-off-by: fhl <2410591650@qq.com>
Signed-off-by: fhl2000 <63384265+fhl2000@users.noreply.github.com>
Signed-off-by: Lucas Wilkinson <lwilkins@redhat.com>
Signed-off-by: Lucas Wilkinson <LucasWilkinson@users.noreply.github.com>
Co-authored-by: Luka Govedič <ProExpertProg@users.noreply.github.com>
Co-authored-by: Lucas Wilkinson <lwilkins@redhat.com>
Co-authored-by: Lucas Wilkinson <LucasWilkinson@users.noreply.github.com>
 2025-08-15 10:01:39 -04:00
Yongye Zhu
39cd09dc86
[Bugfix] use flash attn on sm90 (#22933) 
Signed-off-by: Yongye Zhu <zyy1102000@gmail.com>
Co-authored-by: Michael Goin <mgoin64@gmail.com>
 2025-08-14 16:37:22 -07:00
Michael Goin
b1361c7273
[Bugfix] Fix default enable for CUTLASS MLA on SM100 (#22738) 
Signed-off-by: mgoin <mgoin64@gmail.com>
 2025-08-12 21:22:05 -07:00
Woosuk Kwon
71683ca6f6
[V0 Deprecation] Remove multi-step scheduling (#22138) 
Signed-off-by: Woosuk Kwon <woosuk.kwon@berkeley.edu>
Signed-off-by: Woosuk Kwon <woosuk@thinkingmachines.ai>
 2025-08-12 20:18:39 -07:00
Yongye Zhu
007dd90859
[gpt-oss] Enable gpt-oss on ampere (#22714) 
Signed-off-by: Yongye Zhu <zyy1102000@gmail.com>
 2025-08-12 03:21:44 -07:00
Woosuk Kwon
98a3a81024
[ROCm] Add attention sink to use_rocm_custom_paged_attention (#22329) 
Signed-off-by: Woosuk Kwon <woosuk.kwon@berkeley.edu>

Co-authored-by: LiuXiaoxuanPKU <lilyliupku@gmail.com>
Co-authored-by: simon-mo <xmo@berkeley.edu>
Co-authored-by: Chen Zhang <zhangch99@outlook.com>
Co-authored-by: Hongxia Yang <62075498+hongxiayang@users.noreply.github.com>
Co-authored-by: Minseok Lee <47620120+minseokl@users.noreply.github.com>
Co-authored-by: Yongye Zhu <zyy1102000@gmail.com>
 2025-08-05 23:30:38 -07:00
Giancarlo Delfin
469b3ffaaa
[V1] port xformers backend to v1 (#21342) 
Signed-off-by: Giancarlo Delfin <gdelfin@meta.com>
 2025-08-05 10:04:46 -07:00
Giancarlo Delfin
aa7012eb6d
Add tree attention backend for v1 (part 1) (#20401) 
Signed-off-by: Giancarlo Delfin <gdelfin@meta.com>
 2025-08-03 22:13:26 -07:00
vllmellm
d3a6f2120b
[FEAT][ROCm] Enable running Flash Attention as ViT attn backend for Qwen-VL models on ROCm platform. (#22069) 
Signed-off-by: tjtanaavllm <tunjian.tan@amd.com>
Signed-off-by: vllmellm <vllm.ellm@embeddedllm.com>
Co-authored-by: tjtanaavllm <tunjian.tan@amd.com>
 2025-08-01 23:53:18 -07:00
Michael Goin
61445453df
[UX] Rename CUTLASS_MLA_VLLM_V1 to CUTLASS_MLA (#21966) 
Signed-off-by: mgoin <mgoin64@gmail.com>
 2025-07-30 20:40:34 -07:00
wenxindongwork
8f0d516715
[TPU] Support Pathways in vLLM (#21417) 
Signed-off-by: wenxindongwork <wenxindong@google.com>
 2025-07-30 10:02:12 -07:00
Kunshang Ji
05cbbe20c5
[XPU] use ZE_AFFINITY_MASK for device select on xpu (#21815) 
Signed-off-by: Kunshang Ji <kunshang.ji@intel.com>
 2025-07-30 03:56:14 +00:00
Chaojun Zhang
ec261b0291
[XPU] IPEX-optimized Punica Wrapper on XPU (#21703) 
Signed-off-by: chzhang <chaojun.zhang@intel.com>
Co-authored-by: Jee Jee Li <pandaleefree@gmail.com>
 2025-07-28 16:43:37 +00:00
Alexander Matveev
8f605ee309
[Attention] Make CutlassMLA the default backend for SM100 (blackwell) (#21626) 
Signed-off-by: Alexander Matveev <amatveev@redhat.com>
Signed-off-by: mgoin <mgoin64@gmail.com>
Co-authored-by: mgoin <mgoin64@gmail.com>
 2025-07-27 20:13:00 +00:00
elvischenv
2dec7c1a5d
[Bugfix][CUDA] fixes CUDA FP8 kv cache dtype supported (#21420) 
Signed-off-by: elvischenv <219235043+elvischenv@users.noreply.github.com>
 2025-07-22 20:34:50 -07:00
Varun Sundar Rabindranath
8425f785ad
[Misc] DeepEPHighThroughtput - Enable Inductor pass (#21311) 
Signed-off-by: Varun Sundar Rabindranath <vsundarr@redhat.com>
Co-authored-by: Varun Sundar Rabindranath <vsundarr@redhat.com>
 2025-07-21 23:35:45 -07:00
Konrad Zawora
c17231e827
Fix kv_cache_dtype handling for out-of-tree HPU plugin (#21302) 
Signed-off-by: Konrad Zawora <kzawora@habana.ai>
Signed-off-by: Chendi.Xue <chendi.xue@intel.com>
Co-authored-by: Chendi.Xue <chendi.xue@intel.com>
 2025-07-21 23:35:14 -07:00
Li, Jiang
a15a50fc17
[CPU] Enable shared-memory based pipeline parallel for CPU backend (#21289) 
Signed-off-by: jiang1.li <jiang1.li@intel.com>
 2025-07-21 09:07:08 -07:00
Chengji Yao
3a1d8940ae
[TPU] support fp8 kv cache quantization (#19292) 
Signed-off-by: Chengji Yao <chengjiyao@google.com>
 2025-07-20 03:01:00 +00:00
Woosuk Kwon
752c6ade2e
[V0 Deprecation] Deprecate BlockSparse Attention & Phi3-Small (#21217) 
Signed-off-by: Woosuk Kwon <woosuk.kwon@berkeley.edu>
 2025-07-19 13:53:17 -07:00
Li, Jiang
e3a0e43d7f
[bugfix] Fix auto thread-binding when world_size > 1 in CPU backend and refactor code (#21032) 
Signed-off-by: jiang1.li <jiang1.li@intel.com>
 2025-07-19 05:13:55 -07:00
Woosuk Kwon
dd572c0ab3
[V0 Deprecation] Remove V0 Spec Decode workers (#21152) 
Signed-off-by: Woosuk Kwon <woosuk.kwon@berkeley.edu>
 2025-07-18 21:47:50 -07:00
Woosuk Kwon
54cf1cae62
[Misc] Do not print async output warning for v1 (#21151) 
Signed-off-by: Woosuk Kwon <woosuk.kwon@berkeley.edu>
 2025-07-17 21:57:02 -07:00
Woosuk Kwon
4de7146351
[V0 deprecation] Remove V0 HPU backend (#21131) 
Signed-off-by: Woosuk Kwon <woosuk.kwon@berkeley.edu>
 2025-07-17 16:37:36 -07:00
Alexander Matveev
8cdc371217
SM100 Cutlass MLA decode with unrestricted num_heads (< 128) for DeepSeek TP (#20769) 
Signed-off-by: Alexander Matveev <amatveev@redhat.com>
 2025-07-15 01:06:38 +00:00
Cyrus Leung
e8cc53af5e
[Misc] Log the reason for falling back to FlexAttention (#20699) 
Signed-off-by: DarkLight1337 <tlleungac@connect.ust.hk>
 2025-07-14 04:16:51 -07:00
Congcong Chen
2c11a738b3
[Model] New model support for microsoft/Phi-4-mini-flash-reasoning (#20702) 
Signed-off-by: Congcong Chen <congcongchen@microsoft.com>
 2025-07-12 06:02:10 -07:00
Pavani Majety
7bd4c37ae7
[Core] Add Flashinfer TRTLLM Backend for Flashinfer decode path (SM100). (#19825) 
Signed-off-by: Pavani Majety <pmajety@nvidia.com>
Signed-off-by: mgoin <mgoin64@gmail.com>
Co-authored-by: shuw <shuw@nvidia.com>
Co-authored-by: mgoin <mgoin64@gmail.com>
 2025-07-11 09:23:23 +00:00
Gregory Shtrasberg
5b8366b61a
[ROCm][Regression] Remove tensor creation that harms performance on ROCm (#20741) 
Signed-off-by: Gregory Shtrasberg <Gregory.Shtrasberg@amd.com>
 2025-07-10 09:22:23 -07:00
Harry Mellor
3482fd7e4e
[Doc] Add engine args back in to the docs (#20674) 
Signed-off-by: Harry Mellor <19981378+hmellor@users.noreply.github.com>
 2025-07-10 08:02:40 -07:00
Nick Hill
ffbcc9e757
[BugFix] Fix VllmConfig() construction on all platforms (#20695) 
Signed-off-by: Nick Hill <nhill@redhat.com>
 2025-07-10 07:00:20 +00:00
Liangliang Ma
a3e4e85ece
[XPU][CI] enhance xpu test support (#20652) 
Signed-off-by: Ma, Liangliang <liangliang.ma@intel.com>
Co-authored-by: zhenwei-intel <zhenweiliu@habana.ai>
 2025-07-09 16:53:09 +00:00